1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a flip-flop circuit.
2. Description of Related Art
Heretofore, flip-flop circuits have been broadly used in integrated circuits such as LSI. For the purpose of increasing the performance of integrated circuits, high speed operating flip-flop circuits have hitherto been proposed. Semiconductor integrated circuit devices constituted of such a high speed operating flip-flop circuit include one proposed in an article (Borivoje Nikolic, VojinG. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, and Michael Ming-Tak Leung, “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 35, NO. 6, June 2000 p876-p884) (hereinafter referred to as Document 1).
In the semiconductor integrated circuit device proposed in Document 1, however, due to the amount of electric charges accumulated in parasitic capacitance occurring on a path extending from a power source terminal to a reference voltage terminal in a signal generation circuit, speeding up of operation may be limited, thus causing a problem.
Further, in the semiconductor integrated circuit device proposed in Document 1, due to a status holding circuit, disposed in a latch circuit, for holding the status of output signal, the operating speed when the status of output signal is varied, may be reduced, thus causing a problem.